The level standards which are commonly used currently comprise TTL, CMOS, LVTTL, LVCMOS, ECL, or the like. Besides, the level standards like LVDS, GTL, PGTL, CML, HSTL, which have a relatively high speed of data transmission, are also in use. CML level is the most simple among all the high speed data interfaces. In the CML level, the input and output are matched with each other, thus reducing peripheral devices and making it suitable for operating at higher frequency bands. The CML interface typically has an output circuit including a differential pair. The resistance value of the collector of the differential pair is 50Ω. The switch between the high and low level of the output signal is realized by the switching control of the differential pair which has a common emitter. The constant current source from the emitter of the differential pair to the ground typically has a value of 16 mA. Provided that the output load of CML is a pull-up resistor of 50Ω, the single-ended CML output signal has a swing of VCC˜VCC−0.4 V. In this case, the differential output signal has such a small swing of 800 mV that the power consumption is very low. The CML interface level has a power consumption lower than ½ of ECL, while it has a differential signal interface with similar characteristics with ECL and LVDS.
In a high speed parallel-serial conversion circuit, the clock input over 3 GHz is always performed in a CML mode, while the parallel-serial conversion circuit at a lower frequency is realized by digital circuits. Thus there is a need for a circuit for converting CML into CMOS. In the whole process of high speed parallel-serial conversion, it is generally required that the delay of clock should not exceed a clock cycle. Therefore, it is required that the delay in the CML-CMOS circuit should be as short as possible. A conventional circuit is shown in FIG. 1. In the paper of Tondo, D. F. and Lopez, R. R. from Argentina, “A low-power, high-speed CMOS/CML 16:1 serializer”, Micro-Nanoelectronics, Technology and Applications, 2009. EAMTA 2009 1-2 Oct. 2009, page(s): 81-86, a CML-CMOS clock signal conversion circuit configuration is proposed which is now most widely used. The CML to CMOS conversion circuit comprises a first differential unit including a first differential transistor M1 and a second differential transistor M2; a second differential unit including a third differential transistor M3 and a fourth differential transistor M4; an amplifier including transistors M5 and M6; and an output unit comprising a series connection of a first inverter and a second inverter. The specific signal conversion circuit diagrams for a 65 nm and 45 nm process are shown in FIG. 2a, FIG. 2b, respectively.